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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8315ECVRAGDA датащи(PDF) 60 Page - Freescale Semiconductor, Inc |
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MPC8315ECVRAGDA датащи(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 112 page  MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 60 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8315E SerDes reference clock input’s DC requirement. Figure 46. Single-Ended Connection (Reference Only) 15.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. 50 Ω 50 Ω SD_REF_CLK SD_REF_CLK Clock Driver 100 Ω differential PWB trace SerDes Refer. CLK Receiver Clock Driver CLK_Out CLK_Out LVPECL CLK Driver Chip R2 R2 R1 MPC8315E R1 10 nF 10 nF 50 Ω 50 Ω SD_REF_CLK SD_REF_CLK 100 Ω differential PWB trace SerDes Refer. CLK Receiver Clock Driver CLK_Out Single-Ended CLK Driver Chip MPC8315E 33 Ω Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. 50 Ω |
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