MPC8315ECVRAGDA datasheet(98/112 Pages) FREESCALE

98 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

Table 72 provides the operating frequencies for the TEPBGA II under recommended operating conditions

(see Table 2).

24.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 73 shows the multiplication factor

encodings for the system PLL.

NOTE

If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL

VCO frequency = (CSB frequency)

× (System PLL VCO Divider).

If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO

frequency = 2

× (CSB frequency) × (System PLL VCO Divider).

The VCO divider needs to be set properly so that the System PLL VCO

frequency is in the range of 450–750 MHz.

Table 71. Configurable Clock Units

Unit

Default Frequency

Options

eTSEC1

csb_clk

Off,

csb_clk, csb_clk/2, csb_clk/3

eTSEC2

csb_clk

Off,

csb_clk, csb_clk/2, csb_clk/3

Security Core, I2C, SAP, TPR

csb_clk

Off,

csb_clk, csb_clk/2, csb_clk/3

USB DR

csb_clk

Off,

csb_clk, csb_clk/2, csb_clk/3

PCI and DMA complex

csb_clk

Off,

csb_clk

PCIe

csb_clk

Off,

csb_clk

Serial ATA

csb_clk

Off,

csb_clk, csb_clk/2, csb_clk/3

Table 72. Operating Frequencies for TEPBGA II

Characteristic1

Max Operating Frequency

Unit

e300 core frequency (

core_clk)400

MHz

Coherent system bus frequency (

csb_clk)133

MHz

DDR1/2 memory bus frequency (MCK)2

133

MHz

Local bus frequency (LCLK

n)3

MHz

PCI input frequency (SYS_CLKIN or PCI_CLK)

24-66

MHz

Notes:

1. The SYS_CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting

csb_clk,

MCK, LCLK[0:1], and

core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The DDR data rate is 2x the DDR memory bus frequency.

3. The local bus frequency is 1/2, 1/4, or 1/8 of the

lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x

the

csb_clk frequency (depending on RCWL[LBIUCM]).

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