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MPC8315ECVRAGDA датащи(PDF) 61 Page - Freescale Semiconductor, Inc |
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MPC8315ECVRAGDA датащи(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 112 page ![]() MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 61 High-Speed Serial Interfaces (HSSI) Table 52 describes some AC parameters common to SGMIIPCI Express protocols. Figure 47. Differential Measurement Points for Rise and Fall Time Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching Table 52. SerDes Reference Clock Common AC Parameters At recommended operating conditions with XCOREVDD= 1.0V ± 5% Parameter Symbol Min Max Unit Notes Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3 Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3 Differential Input High Voltage VIH +200 — mV 2 Differential Input Low Voltage VIL — –200 mV 2 Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK) matching Rise-Fall Matching —20 % 1, 4 Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 47. 4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 48. VIH = +200 VIL = –200 0.0 V SDn_REF_CL K minus SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK |
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