MPC8315ECVRAGDA datasheet(28/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 12 shows the MII receive AC timing diagram.

Figure 12. MII Receive AC Timing Diagram RMII AC Timing Specifications

9.2.2

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

9.2.2.1

RMII Transmit AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications. Table 27 provides the

RMII transmit AC timing specifications.

Table 27. RMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 300 mv

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

REF_CLK clock

tRMX

—20

—

REF_CLK duty cycle

tRMXH/tRMX

—

REF_CLK to RMII data TXD[1:0], TX_EN delay

tRMTKHDX

—

REF_CLK data clock rise VIL(min) to VIH(max)

tRMXR

1.0

—

4.0

REF_CLK data clock fall VIH(max) to VIL(min)

tRMXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX

symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid

(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock

of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

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