MPC8315ECVRAGDA datasheet(16/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Clock Input Timing

5.1

DC Electrical Characteristics

Table 6 provides the clock input (SYS_CLKIN/PCI_SYNC_IN) DC timing specifications for the

MPC8315E.

5.2

AC Electrical Characteristics

The primary clock source for the MPC8315E can be one of two inputs, SYS_CLKIN or PCI_CLK,

depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock

input (SYS_CLKIN/PCI_CLK) AC timing specifications for the MPC8315E.

Table 6. SYS_CLKIN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.4

NVDD + 0.3

Input low voltage

—

VIL

-0.3

0.4

SYS_CLKIN input current

0 V

≤VIN ≤ NVDD

IIN

—±10

μA

SYS_CR_CLKIN input current

0 V

≤VIN ≤ NVDD

IIN

—±40

μA

PCI_SYNC_IN input current

0 V

≤VIN ≤ NVDD

IIN

—±10

μA

RTC_CLK input current

0 V

≤VIN ≤ NVDD

IIN

—±10

μA

USB_CLK_IN input current

0 V

≤ VIN ≤ NVDD

IIN

—±10

μA

USB_CR_CLK_IN input current

0 V

≤VIN ≤ NVDD

IIN

—±40

μA

SATA_CLK_IN input current

0 V

≤VIN ≤ NVDD

IIN

—±10

μA

Table 7. SYS_CLKIN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYS_CLKIN/PCI_CLK frequency

fSYS_CLKIN

—

MHz

1, 6, 7

SYS_CLKIN/PCI_CLK cycle time

tSYS_CLKIN

—

41.6

SYS_CLKIN/PCI_CLK rise and fall time

tKH, tKL

0.6

—

1.2

2, 6

SYS_CLKIN/PCI_CLK duty cycle

tKHK/tSYS_CLKIN

—

3, 6

SYS_CLKIN/PCI_CLK jitter

—

±150

4, 5, 6

Notes:

1. Caution: The system, core, and security block must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYS_CLKIN/PCI_CLK are measured at 0.4 and 2.4 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set

low to allow cascade-connected PLL-based devices to track SYS_CLKIN drivers with the specified jitter.

6. The parameter names PCI_CLK and PCI_SYNC_IN are used interchangeably in this document.

7. Spread spectrum is allowed upto 1% down-spread at 33kHz.(max. rate).

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