MPC8315ECVRAGDA datasheet(53/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 37 shows the PCI output AC timing conditions.

Figure 37. PCI Output AC Timing Measurement Condition

15 High-Speed Serial Interfaces (HSSI)

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference

circuits are also shown.

15.1

Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (TXn and TXn) or a receiver input

(RXn and RXn). Each signal swings between A Volts and B Volts where A > B.

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

1. Single-Ended Swing

The transmitter output signals and the receiver input signals TXn, TXn, RXn and RXn each have

a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s Single-Ended

Swing.

2. Differential Output Voltage, VOD (or Differential Output Swing):

The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of

the two complimentary output voltages: VTXn – VTXn. The VOD value can be either positive or

negative.

3. Differential Input Voltage, VID (or Differential Input Swing):

The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the

two complimentary input voltages: VRXn – VRXn. The VID value can be either positive or negative.

4. Differential Peak Voltage, VDIFFp

CLK

Output Delay

tPCKHOV

High-Impedance

tPCKHOZ

Output

tPCKHOX

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