MPC8315ECVRAGDA datasheet(51/112 Pages) FREESCALE

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MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

PCI

14.1

PCI DC Electrical Characteristics

Table 49 provides the DC electrical characteristics for the PCI interface.

14.2

PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or

PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8315E is configured

as a host or agent device. Table 50 shows the PCI AC timing specifications at 66 MHz.

Table 49. PCI DC Electrical Characteristics 1

Parameter

Symbol

Test Condition

Min

Max

Unit

High-level input voltage

VIH

VOUT ≥ VOH (min) or

0.5 x NVDD

NVDD + 0.3

Low-level input voltage

VIL

VOUT ≤ VOL (max)

–0.5

0.3

× NVDD

High-level output voltage

VOH

NVDD = min,

IOH = –500 μA

0.9 x NVDD

—

Low-level output voltage

VOL

NVDD = min,

IOL = 1500 μA

—

0.1 x NVDD

Input current

IIN

0 V

≤ VIN ≤ NVDD

—

± 10

μA

Note:

1. Note that the symbol VIN, in this case, represents the NVIN symbol referenced in Table 1 and Table 2.

Table 50. PCI AC Timing Specifications at 66 MHz

Parameter

Symbol 1

Min

Max

Unit

Notes

Clock to output valid

tPCKHOV

—6.0

Output hold from clock

tPCKHOX

1—

Clock to output high impedance

tPCKHOZ

—14

2, 3

Input setup to clock

tPCIVKH

3.3

—

2, 4

Input hold from clock

tPCIXKH

0—

2, 4

Notes:

1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN

clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect

to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the

PCI 2.3 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

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