910GL datasheet(176/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

176

Datasheet

9.1.3

PCICMD2—PCI Command (D2:F0)

PCI Device:

Address Offset:

04h

Default Value:

0000h

Access:

RO, R/W

Size:

16 bits

This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The

PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.

Bit

Access &

Default

Description

15:11

Reserved

R/W

Interrupt Disable: This bit disables the device from asserting INTx#.

0 = Enable the assertion of this device’s INTx# signal.

1 = Disable the assertion of this device’s INTx# signal. DO_INTx messages will

not be sent to the DMI.

Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.

SERR Enable (SERRE): Not Implemented. Hardwired to 0.

Address/Data Stepping Enable (ADSTEP): Not Implemented. Hardwired to 0.

Parity Error Enable (PERRE): Not Implemented. Hardwired to 0. Since the IGD

belongs to the category of devices that does not corrupt programs or data in

system memory or hard drives, the IGD ignores any parity error that it detects

and continues with normal operation.

Video Palette Snooping (VPS): This bit is hardwired to 0 to disable snooping.

Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does

not support memory write and invalidate commands.

Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special

cycles.

R/W

Bus Master Enable (BME):

0 = Disable IGD bus mastering.

1 = Enable the IGD to function as a PCI compliant master.

R/W

Memory Access Enable (MAE): This bit controls the IGD’s response to memory

space accesses.

0 = Disable.

1 = Enable.

R/W

0 b

I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space

accesses.

0 = Disable.

1 = Enable.

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