910GL datasheet(107/426 Pages) INTEL

номер детали	910GL

подробное описание детали	Express Chipset

PDF	426 Pages

Scroll/Zoom	100%

производитель	INTEL [Intel Corporation]

домашняя страница	http://www.intel.com

Logo

107 / 426 page

MCHBAR Registers

Datasheet

107

5.1.16

C1DRA2—Channel B DRAM Rank 2,3 Attribute

MMIO Range:

MCHBAR

Address Offset:

189h

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DRA0.

5.1.17

C1DCLKDIS—Channel B DRAM Clock Disable

MMIO Range:

MCHBAR

Address Offset:

18Ch

Default Value:

00h

Access:

R/W

Size:

8 bits

The operation of this register is detailed in the description for register C0DCLKDIS.

5.1.18

C1BNKARC—Channel B Bank Architecture

MMIO Range:

MCHBAR

Address Offset:

18Eh

Default Value:

0000h

Access:

R/W

Size:

16 bits

The operation of this register is detailed in the description for register C0BNKARC.

5.1.19

C1DRT1—Channel B DRAM Timing Register 1

MMIO Range:

MCHBAR

Address Offset:

194h

Default Value:

900122h

Access:

R/W

Size:

32 bits

The operation of this register is detailed in the description for register C0DRT1.

5.1.20

C1DRC0—Channel B DRAM Controller Mode 0

MMIO Range:

MCHBAR

Address Offset:

1A0h

Default Value:

00000000h

Access:

R/W

Size:

32 bits

The operation of this register is detailed in the description for register C0DRC0.

910GL датащи(PDF) 107 Page - Intel Corporation

910GL датащи(HTML) 107 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL