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TS68230 датащи(PDF) 47 Page - STMicroelectronics |
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TS68230 датащи(HTML) 47 Page - STMicroelectronics |
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47 / 61 page ![]() 5.2.4.2. External Clock. This configuration allows measurement (counting) of the number of input pulses occurring in an interval in which the counter is enabled. The TIN input pin provides the input pulses. Generally the TOUT and TIACK pins are not used. This configuration is similar to the elapsed time measurement/system clock configuration except that the TIN pin is used to provide the input frequen- cy. It can be connected to a simple oscillator and the same methods could be used. Alternately, it could be gated off and on externally and the number of cy- cles occurring while in the run state can be counted. However, minimum pulse width high and low speci- fications must be met. 5.2.5. DEVICE WATCHDOG. This configuration provides the watchdog function needed in many systems. The TIN pin is the timer input whose period at the high (one) level is to be checked. Once allowed by the processor, the TIN in- put pin controls the run/halt mode. The TOUT pin is connected to external circuitry requiring notification when the TIN pin has been asserted longer than the programmed time. The TIACK pin (timer interrupt acknowledge) is only needed if the TOUT pin is connected to the interrupt circuitry. The processor loads the counter preload register and timer control register, and then enables the ti- mer. When the TIN input is asserted (one, high) the timer transfers the contents of the counter preload register to the counter and begins counting. If the TIN input is negated before zero detect is reached, the TOUT output and the ZDS status bit remain ne- gated. If zero detect is reached while the TIN input is still asserted, the ZDS status bit is set and the TOUT output is asserted. (The counter rolls over and keeps counting). In either case, when the TIN input is negated the ZDS status bit is zero, the TOUT output is negated, the counting stops, and the pres- caler is forced to all ones (see figure 5.5). 7 6 543 2 1 0 Timer Enable TOUT/TIACK Control * Z.D Control Clock Control 0 0 X 1 0 1 X Changed 76 5 4 32 1 0 Timer Enable TOUT/TIACK Control * Z.D Control Clock Control 1 X 1 1 0 0 1 Changed Figure 5.5 : Device Watchdog Example. TS68230 47/61 |
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