TS68230 datasheet(40/61 Pages) STMICROELECTRONICS

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Table 4.3 : PCDR Hardware Accesses.

Port C Function

Alternate Function

Operation

PCDDR = 0

PCDDR = 1

PCDDR = 0

PCDDR = 1

Read Port C Data

Output Register

Write Port C Data

Output Register,

Buffer Disabled

Output Register,

Buffer Enabled

Output Register

ta direction register indicates the input or output di-

rection. The port C data register is single buffered for

output pins and non-latched for input pins. These

conditions are summarized in table 4.3.

Note that two additional useful benefits result from

this structure. First, it is possible to directly read the

state of a dual-function pin while used for the non-

port C function. Second, it is possible to generate

program controlled transitions on alternate-function

pins by switching back to the port C function and wri-

ting to the PCDR.

This register is readable and writable at all times and

operation is independent of the chosen PI/T mode.

The port C data register is not affected by the asser-

tion of the RESET pin.

4.7. PORT ALTERNATE REGISTERS

The following paragraphs describe the port alter-

nate registers.

4.7.1. PORT A ALTERNATE REGISTER (PAAR).

The port A alternate register is an alternate register

for reading the port A pins. It is a read-only address

and no other PI/T condition is affected. In all modes,

the instantaneous pin level is read and no input lat-

ching is performed except at the data bus interface.

Writes to this address are answered with DTACK,

but the data is ignored.

4.7.2. PORT B ALTERNATE REGISTER (PBAR).

The port B alternate register is an alternate register

for reading the port B pins. It is a read-only address

and no other PI/T condition is affected. In all modes,

the instantaneous pin level is read and no input lat-

ching is performed except at the data bus interface.

Writes to this address are answered with DTACK,

but the data is ignored.

4.8. PORT STATUS REGISTER (PSR)

The port status register contains information about

handshake pin activity. Bits 7-4 show the instanta-

neous level of the respective handshake pin, and are

independent of the handshake pin sense bits in the

port general control register.

Bits 3-0 are the respective status bits referred to throu-

ghout this document. Their interpretation depends on

the programmed mode/submode of the PI/T. For bits

3-0 a one is the active or asserted state.

4.9. TIMER CONTROL REGISTER (TCR)

The timer control register (TCR) determines all ope-

rations of the timer. Bits 7-5 configure the PC3/TOUT

and PC7/TIACK pins for port C, square wave, vecto-

red interrupt, or autovectored interrupt operation ; bit

4 specifies whether the counter receives data from the

Level

H4S

H3S

H2S

H1S

Level

Timer

Enable

TOUT/TIACK

Control

Z.D

Control

Clock

Control

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