TS68230 datasheet(35/61 Pages) STMICROELECTRONICS

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Programmable Options Mode 3 - Port A Submode XX and Port B Submode XX

PACR

7 6

Port A Submode

X X

Submode XX.

PACR

5 4 3

H2 Control

X X 0

Output pin - interlocked output handshake protocol, H2S status always cleared.

X X 1

Output pin - pulsed output handshake protocol, H2S status always cleared.

PACR

H2 Interrupt Enable

The H2 interrupt is disabled.

The H2 interrupt is enabled.

PACR

H1 SVCRQ Enable

The H1 interrupt and DMA request are disabled.

The H1 interrupt and DMA request are enabled.

PACR

H1 Status Control

The H1 status bit is set when either the port B initial or final output latch can accept new data.

It is clear when both latches are full and cannot accept new data.

The H1S status bit is set when both of the port B output latches are empty. It is clear when at

least one latch is full.

PBCR

7 6

Port B Submode

X X

Submode XX.

PBCR

5 4 3

H4 Control

X X 0

Output pin - interlocked input handshake protocol, H4S is always clear.

X X 1

Output pin - pulsed input handshake, H4S is always clear.

PBCR

H4 Interrupt Enable

The H4 interrupt is disabled.

The H4 interrupt is enabled.

PBCR

H3 SVCRQ Enable

The H3 interrupt and DMA request are disabled.

The H3 interrupt and DMA request are enabled.

PBCR

H3 Status Control

The H3S status bit is set anytime input data is present in the double-buffered input path.

TS68230

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