TS68230 datasheet(33/61 Pages) STMICROELECTRONICS

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PBCR

5 4 3

H4 Control

X X 0

Output pin - interlocked input handshake protocol, H4S is always cleared.

X X 1

Output pin - pulsed input handshake protocol, H4S is always cleared.

PBCR

H4 Interrupt Enable

The H4 interrupt is disabled.

The H4 interrupt is enabled.

Programmable Options Mode 2 - Port A Submode XX and Port B Submode XX (continued)

PBCR

H3 SVCRQ Enable

The H3 interrupt and DMA request are disabled.

The H3 interrupt and DMA request are enabled.

PBCR

H3 Status Control

The H3S status bit is set anytime input data is present in the double-buffered input path.

3.6. MODE 3 - BIDIRECTIONAL 16-BIT MODE

In mode 3, ports A and B are used for bidirectional

16-bit double-buffered transfers. H1 and H2 control

output transfers, while H3 and H4 control input

transfers. H1 and H2 are enabled by the H12 ena-

ble bit while H3 and H4 are enabled by the H34 ena-

ble bit of the port general control register. The

instantaneous direction of data is determined by the

H1 handshake pin, thus, the data direction registers

are not used and have no affect. The port A and port

B submode fields do not affect PI/T operation in

mode 3. Port A and port B output buffers are con-

trolled by the level of H1. When H1 is negated, the

output buffers (all 16) are enabled and the pins drive

the bidirectional port bus. Generally a peripheral will

negate H1 in response to an asserted H2, which in-

dicates that new output data is present in the dou-

ble-buffered latches. Following acceptance of the

data, the peripheral asserts H1, disabling the output

buffers. Other than controlling the output buffers, H1

is edge-sensitive as in other modes. The port A and

port B data direction registers are not used.

3.6.1. DOUBLE-BUFFERED INPUT TRANSFERS.

Port A and B input data that meets the port setup and

hold times is latched on the asserted edge of H3 and

placed in the initial input latch or the final input latch.

H3 is edge-sensitive, and may assume any duty-cy-

cle as long as both high and low minimum times are

observed. The PI/T contains a port status register

whose H3S status bit is set anytime any input data

is present in the double-buffered latches that has not

been read by the bus master. The action of H4 is

programmable and can be programmed as :

1. H4 may be an output pin in the interlocked in-

put handshake protocol. It is asserted when

the port input latches are ready to accept new

data. It is negated asynchronously following

the asserted edge of the H3 input. As soon as

the input latches become ready, H4 is again

asserted. When the input double-buffered

latches are full, H4 remains negated until data

is removed. Thus, anytime the H4 output is as-

serted, new input data may be entered by as-

serting H3. At other times transitions on H3 are

ignored. The H4S status bit is always clear.

When H34 enable in the port general control

2. H4 may be an output pin in the pulsed input

handshake protocol. It is asserted exactly as in

the interlocked input protocol above, but never

remains asserted longer than four clock cycles.

Typically, a four clock cycle pulse is generated.

But in the case that a subsequent H3 asserted

edge occurs before termination of the pulse, H4

is negated asynchronously. Thus, anytime after

the leading edge of the H4 pulse, new data may

be entered in the double-buffered input latches.

The H4 status bit is always clear. When H34 en-

able is clear, H4 is held negated.

TS68230

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