TS68230 datasheet(36/61 Pages) STMICROELECTRONICS

36 / 61 page

PROGRAMMER’S MODEL

This section describes the internal accessible regis-

ter organization as represented in table 1.3 located

at the end of this document and in table 4.1. Address

space within the address map is reserved for future

expansion.

Table 4.1 : PI/T Register Addressing Assignments.

Select Bits

54321

Accessible

Affected by

Reset

Affected by

Read Cycle

Port General Control Register

(PGCR)

00000

R W

Yes

Port Service Request Register

(PSRR)

00001

R W

Yes

Port A Data Direction Register

(PADDR)

00010

R W

Yes

Port B Data Direction Register

(PBDDR)

00011

R W

Yes

Port C Data Direction Register

(PCDDR)

00100

R W

Yes

Port Interrupt Vector Register

(PIVR)

00101

R W

Yes

Port A Control Register

(PACR)

00110

R W

Yes

Port B Control Register

(PBCR)

00111

R W

Yes

Port A Data Register

(PADR)

01000

R W

Port B Data Register

(PBDR)

01001

R W

Port A Alternate Register

(PAAR)

01010

Port B Alternate Register

(PBAR)

01011

Port C Data Register

(PCDR)

01100

R W

Port Status Register

(PSR)

01101

R W*

Yes

Timer Control Register

(TCR)

10000

R W

Yes

Timer Interrupt Vector Register

(TIVR)

10001

R W

Yes

Counter Preload Register High

(CPRH)

10011

R W

Counter Preload Register Middle

(CPRM)

10100

R W

Counter Preload Register Low

(CPRL)

10101

R W

Count Register High

(CNTRH)

10111

Count Register Middle

(CNTRM)

11000

Count Register Low

(CNTRL)

11001

Timer Status Register

(TSR)

11010

R W*

Yes

R = Read.

W = Write.

Throughout this section the following conventions

are maintained :

1. A read from a reserved location in the map re-

sults in a read from the "null register". The null

a normal bus cycle. A write to one of these lo-

cations results in a normal bus cycle, but writ-

ten data is ignored.

2. Unused bits of a defined register are denoted

by "*" and are read as zeros ; written data is i-

gnored.

3. Bits that are unused in the chosen mode/sub-

mode but are used in others are denoted by

"X", and are readable and writable. Their

content, however, is ignored in the chosen

mode/submode.

4. All registers are addressable as 8-bit quanti-

ties. To facilitate operation with the MOVEP

instruction and the DMAC, addresses are or-

dered such that certain sets of registers may

also be accessed as words (two bytes) or long

words (four bytes).

SECTION 4

* A write to this register may perform a special resetting opera-

TS68230

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