TS68230 datasheet(37/61 Pages) STMICROELECTRONICS

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4.1. PORT GENERAL CONTROL REGISTER

(PGCR)

The port general control register controls many of

the functions that are common to the overall opera-

tion of the ports. The PGCR is composed of three

major fields : bits 7 and 6 define the operational

mode of ports A and B and affect operation of the

handshake pins and status bits ; bits 5 and 4 allow

a software-controlled disabling of particular hard-

ware associated with the handshake pins of each

port ; and bits 3-0 define the sense of the hand-

shake pins. The PGCR is always readable and wri-

table.

All bits are reset to zero when the RESET pin is as-

serted.

The port mode control field should be altered only

when the H12 enable and H34 enable bits are zero.

Except when mode is desired (submode 1X), the

port general control register should be written once

to establish the mode with the H12 and H34 bits

clear. Any other necessary control registers can

then be programmed, after which H12 or H34 is set.

In order to enable the respective operation(s), the

port general control register should be written again.

PGCR

7 6

Port Mode Control

0 0

Mode 0 (Unidirectional 8-Bit Mode).

0 1

Mode 1 (Unidirectional 16-Bit Mode).

1 0

Mode 2 (Bidirectional 8-Bit Mode).

1 1

Mode 3 (Bidirectional 16-Bit Mode).

PGCR

H34 Enable

Disabled.

Enabled.

PGCR

H12 Enable

Disabled.

Enabled.

PGCR

0 Handshake Pin Sense

The associated pin is at the high-voltage

level when negated and at the low-

voltage level when asserted.

The associated pin is at the low-voltage

level when negated and at the high-

voltage level when asserted.

4.2. PORT SERVICE REQUEST REGISTER

(PSRR)

The port service request register controls other func-

tions that are common to the overall operation to the

ports. It is composed of four major fields : bit 7 is u-

nused and is always read as zero ; bits 6 and 5 de-

fine whether interrupt or DMA requests are

generated from activity on the H1 and H3 hands-

hake pins ; bits 4 and 3 determine whether two dual-

function pins operate as port C or port interrupt

request/acknowledge pins ; and bits 2, 1, and 0

control the priority among all port interrupt sources.

Since bits 2, 1, and 0 affect interrupt operation, it is

recommended that they be changed only when the

affected interrupt(s) is (are) disabled or known to re-

main inactive. The PSRR is always readable and

writable.

All bits are reset to zero when the RESET pin is as-

serted.

PSRR

6 5

SVCRQ Select

0 X

The PC4/DMAREQ pin carries the PC4

Port Mode

Control

H34

Enable

H12

Enable

Sense

3 2

SVCRQ

Select

Port Interrupt

Priority Control

Operation

Select

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