TS68230 datasheet(19/61 Pages) STMICROELECTRONICS

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Table 3.1 : Mode 0 Port Data Paths.

Read Port A/B Data Register

Write Port A/B Data Register

Mode

DDR = 0

DDR = 1

DDR = X

0 Submode 00

0 Submode 01

0 Submode 1X

FIL, D. B.

FOL Note 3

FOL, S. B.

IOL/FOL, D. B .

FOL, S. B.

Note 1

Note 2

Note 1

Abbreviations :

IOL - Initial Output Latch

FOL - Final Output Latch

FIL - Final Input Latch

S. B. - Single Buffered

D. B. - Double Buffered

DDR - Data Direction Register

Note 1 : Data is latched in the output data registers (final output latch) and will be single buffered at the pin if

the DDR is 1. The output buffers will be turned off if the DDR is 0.

Note 2 : Data is latched in the double-buffered output data registers. The data in the final output latch will

appear on the port pin if the DDR is a 1.

Note 3 : The output drivers that connect the final output latch to the pins are turned on

3.3.1. SUBMODE 00 - PIN-DEFINABLE DOUBLE-

BUFFERED

INPUT

SINGLE-BUFFERED

OUTPUT. In mode 0, double-buffered input trans-

fers of up to eight bits are available by programming

submode 00 in the desired port’s control register.

Data that meets the port setup and hold times is lat-

ched on the asserted edge of H1(H3) and is placed

in the initial or final input latch. H1(H3) is edge sen-

sitive and may assume any duty cycle as long as

both high and low minimum times are observed. The

PI/T contains a port status register whose H1S(H3S)

status bit is set anytime any input data that has not

been read by the bus master is present in the dou-

ble-buffered latches. The action of H2(H4) is pro-

grammable. The following options are available :

1. H2(H4) may be an edge-sensitive status input

that is independent of H1(H3) and the transfer

of port data. On the asserted edge of H2(H4),

the H2S(H4S) status bit is set. It is cleared by

either the RESET pin being asserted, writing a

one to the particular status bit in the port status

enable) bit of the port general register is clear.

2. H2(H4) may be a general-purpose output pin

that is always negated. In this case the

H2S(H4S) status bit is always clear.

3. H2(H4) may be a general-purpose output pin

that is always asserted. In this case the

H2S(H4S) status bit is always clear.

4. H2(H4) may be an output pin in the interlocked

input handshake protocol. It is asserted when

the port input latches are ready to accept new

data. It is negated asynchronously following

the asserted edge of the H1(H3) input. As soon

as the input latches become ready, H2(H4) is

again asserted. When the input double-buffe-

red latches are full, H2(H4) remains negated

until data is removed. Thus, anytime the

H2(H4) output is asserted, new input data may

be entered by asserting H1(H3). At other

times, transitions on H1(H3) are ignored. The

H2S(H4S) status bit is always clear. When

H12 enable (H34 enable) in the port general

control register is clear, H2(H4) is held nega-

ted.

5. H2(H4) may be an output pin in the pulsed in-

put handshake protocol. It is asserted exactly

as in the interlocked input protocol above, but

never remains asserted longer than four clock

cycles. Typically, a four clock cycle pulse is ge-

nerated. But in the case of a subsequent

H1(H3) asserted edge occurring before termi-

nation of the pulse, H2(H4) is negated asyn-

chronously. Thus, anytime after the leading

edge of the H2(H4) pulse, new data may be

entered in the double-buffered input latches.

The H2S(H4S) status bit is always clear. When

H12 enable (H34 enable) is clear, H2(H4) is

held negated.

For pins used as outputs, the data path consists of

a single latch driving the output buffer. Data written

to the port’s data register does not affect the opera-

tion of any handshake pin or status bit. Output pins

may be used independently of the input transfers.

However, read bus cycles to the data register do re-

move data from the port. Therefore, care should be

taken to avoid processor instructions that perform

unwanted read cycles.

TS68230

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