TS68230 datasheet(25/61 Pages) STMICROELECTRONICS

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Programmable Options Mode 0 - Port A Submode 1X and Port B Submode 1X (continued)

PBCR

H3 Status Control

H3 is an edge-sensitive status input, H3S is set by an asserted edge of H3.

3.4. MODE 1 - UNIDIRECTIONAL 16-BIT MODE

In mode 1, ports A and B are concatenated to form

a single 16-bit port. The port B submode field

controls the configuration of both ports. The possible

submodes are :

Port B Submode X0 - Pin-Definable Double-Buf-

fered Input or Single-Buffered Output

Port B Submode X1 - Pin-Definable Double-Buf-

fered Output or Non-Latched Input

Handshake pins H3 and H4, configured by program-

ming the port B control register, are associated with

the 16-bit double-buffered transfer. These 16-bit

transfers are enabled by setting the H34 enable bit

in the port general control register (PGCR). Hand-

shake pins H1 and H2 may be used as simple status

inputs not related to the 16-bit data transfer or H2

may be an output. Enabling of the H1 and H2 hands-

hake pins is done by setting the H12 enable bit of

the port general control register. The port A and B

data direction registers operate in each submode.

Along with the submode, they affect the data read

and written at the data register according to table

3.2. The data direction register also enables the out-

put buffer associated with each port pin. The DMA-

REQ pin may be associated only with H3.

Table 3.2 : Mode 1 Port Data Paths.

Read Port A/B Register

Write Port A/B Register

Mode

DDR = 0

DDR = 1

DDR = 0

DDR = 1

1, Port B

Submode X0

1, Port B

Submode X1

FIL, D. B.

FOL

Note 3

FOL

Note 3

FOL, S. B.

Note 2

IOL/FOL, D. B.

Note 1

FOL, S. B.

Note 2

IOL/FOL, D. B.

Note 1

Note 1 : Data written to Port A goes to a temporary latch. When the Port B data register is later written, Port A

data is transferred to IOL/FOL.

Note 2 : Data is latched in the output data registers (final output latch) and will be single buffered at the pin if

the DDR is 1. The output buffers will be turned off if the DDR is 0.

Note 3 : The output drivers that connect the final output latch to the pins are turned on.

Abbreviations :

IOL - Initial Output Latch

FOL - Final Output Latch

FIL - Final Input Latch

S. B. - Single Buffered

D. B. - Double Buffered

DDR - Data Direction Register

Mode 1 can provide convenient high-speed 16-bit

transfers. The port A and port B data registers are

addressed for compatibility with the TS68000 move

peripheral (MOVEP) instruction and with the 68440

direct memory access controller (DMAC). To take

advantage of this, port A should contain the most-

significant byte of data and always be read or written

by the bus master first. The interlocked and pulsed

handshake protocols, status bits, and DMAREQ are

keyed to the access of port B data register in mode

1. Transfers proceed properly with interlocked or

pulsed handshakes when the port B data register is

accessed last.

TS68230

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