SH7721 datasheet(104/1524 Pages) RENESAS

номер детали	SH7721

подробное описание детали	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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производитель	RENESAS [Renesas Technology Corp]

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104 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 42 of 1458

REJ09B0033-0300

2.3

This LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three

system registers, and one program counter.

(1) General Registers

This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to

R7_BANK1 and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB)

bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or

R0_BANK1 to R7_BANK1) are accessed as general registers.

(2) System Registers

This LSI incorporates the multiply and accumulate registers (MACH/MACL) and procedure

mode.

(3) Program Counter

The program counter stores the value obtained by adding 4 to the current instruction address.

(4) Control Registers

This LSI incorporates the status register (SR), global base register (GBR), save status register

(SSR), save program counter (SPC), and vector base register as control register. Only the GBR can

be accessed in user mode. Control registers other than the GBR can be accessed only in privileged

mode.

SH7721 датащи(PDF) 104 Page - Renesas Technology Corp