SH7721 datasheet(53/1524 Pages) RENESAS

53 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page liii of lxii

Tables

Section 1 Overview

Table 1.1

SH7720/SH7721 Features......................................................................................... 2

Table 1.2

Product Lineup (SH7720 Group).............................................................................. 8

Table 1.3

Product Lineup (SH7721 Group).............................................................................. 9

Table 1.4

List of Pin Assignments .......................................................................................... 13

Table 1.5

SH7720/SH7721 Pin Functions .............................................................................. 25

Section 2 CPU

Table 2.1

Virtual Address Space............................................................................................. 40

Table 2.2

Table 2.3

Addressing Modes and Effective Addresses for CPU Instructions......................... 56

Table 2.4

CPU Instruction Formats ........................................................................................ 60

Table 2.5

CPU Instruction Types............................................................................................ 63

Table 2.6

Data Transfer Instructions....................................................................................... 67

Table 2.7

Arithmetic Operation Instructions .......................................................................... 69

Table 2.8

Logic Operation Instructions .................................................................................. 71

Table 2.9

Shift Instructions..................................................................................................... 72

Table 2.10

Branch Instructions ................................................................................................. 73

Table 2.11

System Control Instructions.................................................................................... 74

Table 2.12

Operation Code Map............................................................................................... 77

Section 3 DSP Operating Unit

Table 3.1

CPU Processing Modes .......................................................................................... 83

Table 3.2

Virtual Address Space............................................................................................. 84

Table 3.3

Operation of SR Bits in Each Processing Mode ..................................................... 87

Table 3.4

RS and RE Setting Rule.......................................................................................... 93

Table 3.5

Repeat Control Instructions .................................................................................... 93

Table 3.6

Repeat Control Macros ........................................................................................... 94

Table 3.7

DSP Mode Extended System Control Instructions ................................................. 96

Table 3.8

PC Value during Repeat Control (When RC[11:0]

≥ 2) .........................................99

Table 3.9

Extended System Control Instructions in DSP Mode ........................................... 103

Table 3.10

Overview of Data Transfer Instructions................................................................ 106

Table 3.11

Modulo Addressing Control Instructions.............................................................. 108

Table 3.12

Double Data Transfer Instruction Formats ........................................................... 111

Table 3.13

Single Data Transfer Instruction Formats ............................................................. 112

Table 3.14

Destination Register in DSP Instructions.............................................................. 114

Table 3.15

Source Register in DSP Operations ...................................................................... 115

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