SH7721 datasheet(12/1524 Pages) RENESAS

12 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xii of lxii

3.2.4

DSP Registers ......................................................................................................... 88

3.3

CPU Extended Instructions.................................................................................................. 89

3.3.1

DSP Repeat Control................................................................................................ 89

3.4

DSP Data Transfer Instructions ......................................................................................... 100

3.4.1

General Registers.................................................................................................. 104

3.4.2

DSP Data Addressing ........................................................................................... 106

3.4.3

Modulo Addressing .............................................................................................. 108

3.4.4

Memory Data Formats .......................................................................................... 110

3.4.5

Instruction Formats of Double and Single Transfer Instructions .......................... 111

3.5

DSP Data Operation Instructions....................................................................................... 113

3.5.1

DSP Registers ....................................................................................................... 113

3.5.2

DSP Operation Instruction Set.............................................................................. 118

3.5.3

DSP-Type Data Formats....................................................................................... 123

3.5.4

ALU Fixed-Point Arithmetic Operations.............................................................. 125

3.5.5

ALU Integer Operations ....................................................................................... 131

3.5.6

ALU Logical Operations ...................................................................................... 133

3.5.7

Fixed-Point Multiply Operation............................................................................ 135

3.5.8

Shift Operations .................................................................................................... 137

3.5.9

Most Significant Bit Detection Operation ............................................................ 141

3.5.10 Rounding Operation.............................................................................................. 144

3.5.11 Overflow Protection.............................................................................................. 146

3.5.12 Local Data Move Instruction ................................................................................ 147

3.5.13 Operand Conflict .................................................................................................. 148

3.6

DSP Extended Function Instruction Set............................................................................. 149

3.6.1

CPU Extended Instructions................................................................................... 149

3.6.2

Double-Data Transfer Instructions ....................................................................... 151

3.6.3

Single-Data Transfer Instructions ......................................................................... 152

3.6.4

DSP Operation Instructions .................................................................................. 154

3.6.5

Operation Code Map in DSP Mode ...................................................................... 160

Section 4 Memory Management Unit (MMU).................................................... 165

4.1

Role of MMU .................................................................................................................... 165

4.1.1

MMU of This LSI ................................................................................................. 168

4.2

Register Descriptions ......................................................................................................... 174

4.2.1

Page Table Entry Register High (PTEH).............................................................. 174

4.2.2

Page Table Entry Register Low (PTEL) ............................................................... 175

4.2.3

Translation Table Base Register (TTB) ................................................................ 175

4.2.4

MMU Control Register (MMUCR) ...................................................................... 175

4.3

TLB Functions ...................................................................................................................177

4.3.1

Configuration of the TLB ..................................................................................... 177

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