SH7721 datasheet(27/1524 Pages) RENESAS

27 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xxvii of lxii

26.4.4 Data Format .......................................................................................................... 907

26.4.5 Setting the Display Resolution.............................................................................. 910

26.4.6 Power Management Registers............................................................................... 910

26.4.7 Operation for Hardware Rotation ......................................................................... 915

26.5

Clock and LCD Data Signal Examples .............................................................................. 918

26.6

Usage Notes ....................................................................................................................... 928

26.6.1 Procedure for Halting Access to Display Data Storage VRAM

(Synchronous DRAM in Area 3) .......................................................................... 928

Section 27 A/D Converter....................................................................................929

27.1

Features.............................................................................................................................. 929

27.2

Input Pins ........................................................................................................................... 931

27.3

Register Descriptions ......................................................................................................... 932

27.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 932

27.3.2 A/D Control/Status Registers (ADCSR)............................................................... 933

27.4

Operation ........................................................................................................................... 936

27.4.1 Single Mode.......................................................................................................... 936

27.4.2 Multi Mode ........................................................................................................... 938

27.4.3 Scan Mode ............................................................................................................ 940

27.4.4 Input Sampling and A/D Conversion Time .......................................................... 942

27.4.5 External Trigger Input Timing.............................................................................. 943

27.5

Interrupts............................................................................................................................ 944

27.6

Definitions of A/D Conversion Accuracy.......................................................................... 944

27.7

Usage Notes ....................................................................................................................... 946

27.7.1 Notes on A/D Conversion ..................................................................................... 946

27.7.2 Notes on A/D Conversion-End Interrupt and DMA Transfer ............................... 948

27.7.3 Allowable Signal-Source Impedance.................................................................... 948

27.7.4 Influence to Absolute Accuracy............................................................................ 949

27.7.5 Setting Analog Input Voltage ............................................................................... 949

27.7.6 Notes on Board Design ......................................................................................... 949

27.7.7 Notes on Countermeasures to Noise ..................................................................... 950

Section 28 D/A Converter (DAC)........................................................................953

28.1

Features.............................................................................................................................. 953

28.2

Input/Output Pins ...............................................................................................................954

28.3

Register Descriptions ......................................................................................................... 954

28.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 954

28.3.2 D/A Control Register (DACR) ............................................................................. 955

28.4

Operation ........................................................................................................................... 956

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