SH7721 datasheet(101/1524 Pages) RENESAS

101 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 39 of 1458

REJ09B0033-0300

2.2

Memory Map

2.2.1

Virtual Address Space

The LSI supports 32-bit virtual addresses and accesses system resources using the 4-Gbytes of

virtual address space. User programs and data are accessed from the virtual address space. The

virtual address space is divided into several areas as shown in table 2.1.

(1)

P0/U0 Area

This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user

mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0 areas are

handled as address translatable areas.

If the cache is enabled, access to the P0 or U0 area is cached. If a P0 or U0 address is specified

while the address translation unit is enabled, the P0 or U0 address is translated into a physical

address based on translation information defined by the user.

If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in

user mode, a transition to an address error exception occurs.

(2)

P1 Area

The P1 area is defined as a cacheable but non-address translatable area. Normally, programs

executed at high speed in privileged mode, such as exception processing handlers, which are at the

core of the operating system (OS), are assigned to the P1 area.

(3)

P2 Area

The P2 area is defined as a non-cacheable but non-address translatable area. A reset processing

program to be called from the reset state is described at the start address (H'A0000000) of the P2

area. Normally, programs such as system initialization routines and OS initiation programs are

assigned to the P2 area. To access a part of an on-chip I/O, its corresponding program should be

assigned to the P2 area.

(4)

P3 Area

The P3 area is defined as a cacheable and address translatable area. This area is used if an address

translation is required for a privileged program.

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