SH7721 datasheet(26/1524 Pages) RENESAS

26 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xxvi of lxii

25.9

Usage Notes ....................................................................................................................... 859

25.9.1 Setup Data Reception ........................................................................................... 859

25.9.2 FIFO Clear ............................................................................................................ 859

25.9.3 Overreading/Overwriting of Data Register........................................................... 859

25.9.4 Assigning EP0 Interrupt Sources .......................................................................... 860

25.9.5 FIFO Clear when DMA Transfer is Set ................................................................ 860

25.9.6 Note on Using TR Interrupt .................................................................................. 860

25.9.7 Note on Clock Frequency ..................................................................................... 861

Section 26 LCD Controller (LCDC) ................................................................... 863

26.1

Features.............................................................................................................................. 863

26.2

Input/Output Pins ...............................................................................................................865

26.3

Register Configuration....................................................................................................... 866

26.3.1 LCDC Input Clock Register (LDICKR) ............................................................... 867

26.3.2 LCDC Module Type Register (LDMTR) ............................................................. 868

26.3.3 LCDC Data Format Register (LDDFR)................................................................ 871

26.3.4 LCDC Scan Mode Register (LDSMR) ................................................................. 873

26.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ........... 875

26.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ........... 876

26.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ........... 877

26.3.8 LCDC Palette Control Register (LDPALCR)....................................................... 878

26.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ....................................... 879

26.3.10 LCDC Horizontal Character Number Register (LDHCNR) ................................. 880

26.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ......................................... 881

26.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ............................. 882

26.3.13 LCDC Vertical Total Line Number Register (LDVTLNR).................................. 883

26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ............................................. 884

26.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ....... 885

26.3.16 LCDC Interrupt Control Register (LDINTR) ....................................................... 886

26.3.17 LCDC Power Management Mode Register (LDPMMR) ..................................... 889

26.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR)................................ 891

26.3.19 LCDC Control Register (LDCNTR)..................................................................... 892

26.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)............................ 893

26.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ............. 895

26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) .......................... 896

26.4

Operation ........................................................................................................................... 897

26.4.1 LCD Module Sizes which can be Displayed in this LCDC .................................. 897

26.4.2 Limits on the Resolution of Rotated Displays, Burst Length,

and Connected Memory (SDRAM) ...................................................................... 898

26.4.3 Color Palette Specification ................................................................................... 905

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