SH7721 datasheet(99/1524 Pages) RENESAS

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Section 2

CPU

CPUS3D0S_000020020300

Rev. 3.00 Jan. 18, 2008 Page 37 of 1458

REJ09B0033-0300

Section 2

CPU

2.1

Processing States and Processing Modes

2.1.1

Processing States

This LSI supports four types of processing states: a reset state, an exception handling state, a

program execution state, and a low-power consumption state, according to the CPU processing

states.

(1)

Reset State

In the reset state, the CPU is reset. The LSI supports two types of resets: power-on reset and

manual reset. For details on resets, refer to section 7, Exception Handling.

In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In

manual reset, the register contents of a part of the LSI on-chip modules are retained. For details,

refer to section 37, List of Registers. The CPU internal statuses and registers are initialized both in

power-on reset and manual reset. After initialization, the program branches to address

H'A0000000 to pass control to the reset processing program to be executed.

(2)

Exception Handling State

In the exception handling state, the CPU processing flow is changed temporarily by a general

exception or interrupt exception processing. The program counter (PC) and status register (SR) are

saved in the save program counter (SPC) and save status register (SSR), respectively. The program

branches to an address obtained by adding a vector offset to the vector base register (VBR) and

passes control to the exception processing program defined by the user to be executed. For details

on reset, refer to section 7, Exception Handling.

(3)

Program Execution State

The CPU executes programs sequentially.

(4)

Low-Power Consumption State

The CPU stops operation to reduce power consumption. The power-down mode can be entered by

executing the SLEEP instruction. For details on the power-down mode, refer to section 13, Power-

Down Modes.

Figure 2.1 shows a status transition diagram.

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