SH7721 datasheet(14/1524 Pages) RENESAS

14 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xiv of lxii

Section 6 X/Y Memory ....................................................................................... 213

6.1

Features.............................................................................................................................. 213

6.2

Operation ........................................................................................................................... 214

6.2.1

Access from CPU ................................................................................................. 214

6.2.2

Access from DSP .................................................................................................. 214

6.2.3

Access from Bus Master Module.......................................................................... 215

6.3

Usage Notes ....................................................................................................................... 215

6.3.1

Page Conflict ........................................................................................................ 215

6.3.2

Bus Conflict .......................................................................................................... 215

6.3.3

MMU and Cache Settings..................................................................................... 216

6.3.4

Sleep Mode ........................................................................................................... 216

Section 7 Exception Handling ............................................................................. 217

7.1

Register Descriptions ......................................................................................................... 217

7.1.1

TRAPA Exception Register (TRA) ...................................................................... 218

7.1.2

Exception Event Register (EXPEVT)................................................................... 219

7.1.3

Interrupt Event Register (INTEVT)...................................................................... 219

7.1.4

Interrupt Event Register 2 (INTEVT2)................................................................. 220

7.1.5

Exception Address Register (TEA) ...................................................................... 220

7.2

Exception Handling Function ............................................................................................ 221

7.2.1

Exception Handling Flow ..................................................................................... 221

7.2.2

Exception Vector Addresses ................................................................................. 222

7.2.3

Exception Codes ................................................................................................... 222

7.2.4

Exception Request and BL Bit (Multiple Exception Prevention) ......................... 222

7.2.5

Exception Source Acceptance Timing and Priority .............................................. 223

7.3

Individual Exception Operations ....................................................................................... 227

7.3.1

Resets.................................................................................................................... 227

7.3.2

General Exceptions ............................................................................................... 227

7.3.3

General Exceptions (MMU Exceptions)............................................................... 231

7.4

Exception Processing While DSP Extension Function is Valid......................................... 234

7.4.1

Illegal Instruction Exception and Illegal Slot Instruction Exception .................... 234

7.4.2

CPU Address Error ............................................................................................... 234

7.4.3

Exception in Repeat Control Period ..................................................................... 234

7.5

Usage Notes ....................................................................................................................... 241

Section 8 Interrupt Controller (INTC)................................................................. 243

8.1

Features.............................................................................................................................. 243

8.2

Input/Output Pins ...............................................................................................................245

8.3

Register Descriptions ......................................................................................................... 246

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