SH7721 datasheet(29/1524 Pages) RENESAS

29 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xxix of lxii

Section 31 MultiMediaCard Interface (MMCIF) ..............................................1027

31.1

Features............................................................................................................................ 1027

31.2

Input/Output Pins ............................................................................................................. 1029

31.3

Register Descriptions ....................................................................................................... 1030

31.3.1 Mode Register (MODER)................................................................................... 1031

31.3.2 Command Type Register (CMDTYR)................................................................ 1031

31.3.3 Response Type Register (RSPTYR) ................................................................... 1033

31.3.4 Transfer Byte Number Count Register (TBCR) ................................................. 1036

31.3.5 Transfer Block Number Counter (TBNCR)........................................................ 1037

31.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5).............................................. 1037

31.3.7 Response Registers 0 to 16 and D (RSPR0 to RSPR16 and RSPRD) ................ 1038

31.3.8 Command Start Register (CMDSTRT)............................................................... 1040

31.3.9 Operation Control Register (OPCR) ................................................................... 1041

31.3.10 Command Timeout Control Register (CTOCR) ................................................. 1043

31.3.11 Data Timeout Register (DTOUTR) .................................................................... 1044

31.3.12 Card Status Register (CSTR) .............................................................................. 1045

31.3.13 Interrupt Control Registers 0 and 1 (INTCR0 and INTCR1).............................. 1047

31.3.14 Interrupt Status Registers 0 and 1 (INTSTR0 and INTSTR1) ............................ 1049

31.3.15 Transfer Clock Control Register (CLKON)........................................................ 1053

31.3.16 VDD/Open-Drain Control Register (VDCNT) ................................................... 1054

31.3.17 Data Register (DR) ............................................................................................. 1054

31.3.18 FIFO Pointer Clear Register (FIFOCLR) ........................................................... 1055

31.3.19 DMA Control Register (DMACR) ..................................................................... 1055

31.3.20 Interrupt Control Register 2 (INTCR2)............................................................... 1056

31.3.21 Interrupt Status Register 2 (INTSTR2) ............................................................... 1057

31.4

Operation ......................................................................................................................... 1058

31.4.1 Operations in MMC Mode.................................................................................. 1058

31.5

Operations Using DMAC................................................................................................. 1088

31.5.1 Operation of Read Sequence............................................................................... 1088

31.5.2 Operation of Write Sequence.............................................................................. 1098

31.6

MMCIF Interrupt Sources................................................................................................ 1108

Section 32 SSL Accelerator (SSL) ....................................................................1109

Section 33 User Break Controller (UBC) ..........................................................1111

33.1

Features............................................................................................................................ 1111

33.2

Register Descriptions ....................................................................................................... 1113

33.2.1 Break Address Register A (BARA) .................................................................... 1113

33.2.2 Break Address Mask Register A (BAMRA)....................................................... 1114

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