SH7721 datasheet(42/1524 Pages) RENESAS

42 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xlii of lxii

Section 20 I

2C Bus Interface (IIC)

Figure 20.1 Block Diagram of I2C Bus Interface ....................................................................... 646

Figure 20.2 External Circuit Connections of I/O Pins................................................................ 647

Figure 20.3 I2C Bus Formats ...................................................................................................... 660

Figure 20.4 I2C Bus Timing........................................................................................................ 661

Figure 20.5 Master Transmit Mode Operation Timing (1)......................................................... 662

Figure 20.6 Master Transmit Mode Operation Timing (2)......................................................... 663

Figure 20.7 Master Receive Mode Operation Timing (1) .......................................................... 664

Figure 20.8 Master Receive Mode Operation Timing (2) .......................................................... 665

Figure 20.9 Slave Transmit Mode Operation Timing (1) ........................................................... 666

Figure 20.10 Slave Transmit Mode Operation Timing (2) ......................................................... 667

Figure 20.11 Slave Receive Mode Operation Timing (1)........................................................... 668

Figure 20.12 Slave Receive Mode Operation Timing (2)........................................................... 669

Figure 20.13 Block Diagram of Noise Conceller ....................................................................... 670

Figure 20.14 Sample Flowchart for Master Transmit Mode ...................................................... 671

Figure 20.15 Sample Flowchart for Master Receive Mode ........................................................ 672

Figure 20.16 Sample Flowchart for Slave Transmit Mode......................................................... 673

Figure 20.17 Sample Flowchart for Slave Receive Mode .......................................................... 674

Figure 20.18 The Timing of the Bit Synchronous Circuit .......................................................... 676

Section 21 Serial I/O with FIFO (SIOF)

Figure 21.1 Block Diagram of SIOF .......................................................................................... 680

Figure 21.2 Serial Clock Supply................................................................................................. 709

Figure 21.3 Serial Data Synchronization Timing ....................................................................... 711

Figure 21.4 SIOF Transmit/Receive Timing .............................................................................. 712

Figure 21.5 Transmit/Receive Data Bit Alignment .................................................................... 715

Figure 21.6 Control Data Bit Alignment .................................................................................... 716

Figure 21.7 Control Data Interface (Slot Position)..................................................................... 717

Figure 21.8 Control Data Interface (Secondary FS) ................................................................... 718

Figure 21.9 Example of Transmit Operation in Master Mode.................................................... 721

Figure 21.10 Example of Receive Operation in Master Mode ................................................... 722

Figure 21.11 Example of Transmit Operation in Slave Mode.................................................... 723

Figure 21.12 Example of Receive Operation in Slave Mode ..................................................... 724

Figure 21.13 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 729

Figure 21.14 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 730

Figure 21.15 Transmit and Receive Timing (16-Bit Monaural Data (1))................................... 730

Figure 21.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 731

Figure 21.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 731

Figure 21.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 732

Figure 21.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 732

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