SH7721 datasheet(65/1524 Pages) RENESAS

65 / 1524 page

Section 1

Overview

Rev. 3.00

Jan. 18, 2008

Page 3 of 1458

REJ09B0033-0300

Item

Features

Memory

management unit

(MMU)

• 4-Gbyte address space, 256 address spaces (8-bit ASID)

• Page unit sharing

• Supports multiple page sizes: 1 kbyte or 4 kbytes

• 128-entry, 4-way set associative TLB

• Specifies replacement way by software and supports random replacement

algorithm

• Address assignment allows direct access to TLB contents

Cache memory

• 32-kbyte cache mixing instructions and data

• 512-entry, 4-way set associative, 16-byte block length

• Write-back, write-through, least recent used (LRU) replacement algorithm

• Single-stage write-back buffer

X/Y memory

• User-selectable mapping mechanism

 Fixed mapping for mission-critical realtime applications

 Automatic mapping through TLB for easy to use

• Three independent read/write ports

 8-/16-/32-bit access from CPU

 Up to two 16-bit accesses from DSP

 8-/16-/32-bit access from DMAC

• 8-kbyte RAM for X and Y memory individual (4 kbytes × 4)

Interrupt

controller (INTC)

• Seven external interrupt pins (NMI, IRQ5 to IRQ0)

 NMI: Fall/rise selectable

 IRQ: Fall/rise/high level/low level selectable

• On-chip peripheral interrupt: Sets priority for each module

Bus state

controller (BSC)

• Physical address space is provided to support areas of up to 64 Mbytes and

32 Mbytes.

• Each area allows independent setting of the following functions:

 Bus size (8, 16, or 32 bits). An access wait cycle count with a different

size to be supported is provided for each area.

 Number of access wait cycles. Some areas can be inserted wait cycles

independently in read access and write access.

 Sets of idle wait cycle (for the same or different area)

 Supports SRAM, page mode ROM, SDRAM, and pseudo SRAM (ready

for page mode) by specifying memory to be connected to each area.

 Outputs chip select signals to corresponding areas, such as CS0, CS2 to

CS4, CS5A/CS5B, and CS6A/CS6B

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