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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 270 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 270 Page - Renesas Technology Corp |
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270 / 508 page  Section 9 Timers Rev. 1.00 May 30, 2008 Page 250 of 484 REJ09B0436-0100 Bit 6: Timer overflow flag L (OVFL) Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 OVFL Description 0 Clearing condition: (initial value) After reading OVFL = 1, cleared by writing 0 to OVFL 1 Setting condition: Set when TCG overflows from H'FF to H'00 Bit 5: Timer overflow interrupt enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE Description 0 TCG overflow interrupt request is disabled (initial value) 1 TCG overflow interrupt request is enabled Bit 4: Input capture interrupt edge select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request. Bit 4 IIEGS Description 0 Interrupt generated on rising edge of input capture input signal (initial value) 1 Interrupt generated on falling edge of input capture input signal |
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