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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 269 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 269 Page - Renesas Technology Corp |
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269 / 508 page  Section 9 Timers Rev. 1.00 May 30, 2008 Page 249 of 484 REJ09B0436-0100 (4) Timer Mode Register G (TMG) OVFH CCLR0 CKS1 CKS0 OVFL OVIE IIEGS CCLR1 7 6 543210 0 0000000 R/W* R/W R/W R/W R/W* R/W R/W R/W Bit: Initial value: Read/Write: Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. TMG is initialized to H'00 upon reset. Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is high. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 OVFH Description 0 Clearing condition: (initial value) After reading OVFH = 1, cleared by writing 0 to OVFH 1 Setting condition: Set when TCG overflows from H'FF to H'00 |
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