H838532H datasheet(157/508 Pages) RENESAS

157 / 508 page

Section 6 ROM

Rev. 1.00 May 30, 2008 Page 137 of 484

REJ09B0436-0100

6.5

Flash Memory Programming/Erasing

A software method using the CPU is employed to program and erase flash memory in the on-

board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one

of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify

mode. The programming control program in boot mode and the user program/erase control

program in user program mode use these operating modes in combination to perform

programming/erasing. Flash memory programming and erasing should be performed in

accordance with the descriptions in section 6.5.1, Program/Program-Verify and section 6.5.2,

Erase/Erase-Verify, respectively.

6.5.1

Program/Program-Verify

When writing data or programs to the flash memory, the program/program-verify flowchart shown

in figure 6.4 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to the flash memory without subjecting the chip to

voltage stress or sacrificing program data reliability.

1. Programming must be done to an empty address. Do not reprogram an address to which

programming has already been performed.

2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be

performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the

extra addresses.

3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-

byte reprogramming data area, and a 128-byte additional-programming data area. Perform

reprogramming data computation according to table 6.6, and additional programming data

computation according to table 6.7.

4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or

additional-programming data area to the flash memory. The program address and 128-byte

data are latched in the flash memory. The lower 8 bits of the start address in the flash memory

destination area must be H'00 or H'80.

5. The time during which the P bit is set to 1 is the programming time. Figure 6.8 shows the

allowable programming times.

6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

An overflow cycle of approximately 6.6 ms is allowed.

7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit

is b'0. Verify data can be read in word size from the address to which a dummy write was

performed.

8. The maximum number of repetitions of the program/program-verify sequence of the same bit

is 1,000.

H838532H датащи(PDF) 157 Page - Renesas Technology Corp