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H838532H датащи(PDF) 150 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 150 Page - Renesas Technology Corp |
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150 / 508 page ![]() Section 6 ROM Rev. 1.00 May 30, 2008 Page 130 of 484 REJ09B0436-0100 Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified. 6.3.3 Erase Block Register (EBR) Bit Initial value Read/Write 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 0 EB0 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be erased. Other blocks change to the erase-protection state. See table 6.2 for the method of dividing blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a block. Table 6.2 Division of Blocks to Be Erased EBR Bit Name Block (Size) Address 0 EB0 EB0 (1 Kbyte) H'0000 to H'03FF 1 EB1 EB1 (1 Kbyte) H'0400 to H'07FF 2 EB2 EB2 (1 Kbyte) H'0800 to H'0BFF 3 EB3 EB3 (1 Kbyte) H'0C00 to H'0FFF 4 EB4 EB4 (28 Kbytes) H'1000 to H'7FFF 5 EB5 EB5 (16 Kbytes) H'8000 to H'BFFF 6 EB6 EB6 (8 Kbytes) H'C000 to H'DFFF 7 EB7 EB7 (4 Kbytes) H'E000 to H'EFFF |
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