MPF0900AMMA2ES datasheet(124/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

OTP_LDOx_UVTH[2:0]

UV threshold

000

96.5 %

001

96.0 %

010

95.5 %

011

95.0 %

100

94.5 %

101

94.0 %

110

93.5 %

111

93.0 %

Table 160. LDOx UV threshold configuration bits

The overvoltage monitoring threshold for the LDO regulators is set in the OTP registers via the

OTP_xxx_OVTH[2:0] bits.

OTP_LDOx_OVTH[2:0]

OV threshold

000

103.5 %

001

104.0 %

010

104.5 %

011

105.0 %

100

105.5 %

101

106.0 %

110

106.5 %

111

107.0 %

Table 161. LDOx OV threshold configuration bits

The UV and OV thresholds represent percentages of the nominal voltage programmed on each regulator.

Settng the thresholds ensures that an undervoltage condition below the selected UV threshold or an

overvoltage condition above the selected OV threshold will always be detected by the VMON circuit.

OV/UV monitoring for all SWx and LDOx regulator are provided with a hysteresis to prevent multiple fault

detection on borderline conditions, however, because the SW regulators offer very tight monitoring as low

as 2.5% of the nominal voltage selection, the PF09 provides the OTP_SWx_2P5TH_HYS bits to disable the

hysteresis in the +/-2.5% monitoring threshold in order to avoid potential overlapping conditions between the

voltage accuracy and the monitoring threshold accuracy specifications.

OTP_SWx_2P5TH_HYS

Hysteresis on 2.5 % OV/UV threshold

Disabled

Enabled

Table 162. Hysteresis on 2.5 % OV/UV threshold configuration bits

On part numbers using the 2.5% OV/UV monitoring threshold without hysteresis, it is recommended to select

larger OV/UV debounce times to minimize multiple fault detection due to oscillating borderline conditions.

The debounce time required for an OV condition to be detected can be programmed in the functional register

via the OV_DBNC[1:0] bits. The OV debounce time is global for all voltage monitors, and, by default, the

configuration, is reset to the lowest condition (0b00) at power up. The MCU must configure the actual value

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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