MPF0900AMMA2ES datasheet(157/205 Pages) NXP

157 / 205 page

NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

14.7 FCCU monitoring

The fault conllection and control unit (FCCU) input pins are in charge of monitoring HW failures from an NXP

MCU or other protocols compatible with other MCU.

In devices targeting a high safety integrity level where the FCCU block is available, the FCCU configuration is

set in the OTP registers via the OTP_FCCUx_MODE[1:0] bits.

In system using a compatible NXP MCU with an FCCU interface, the FCCU0 and FCCU1 are connected to

EOUT[0] and EOUT[1] outputs in the MCU. FCCU0 and FCCU1 can be used in bistable mode, or as a single

input depending on the targeted safety integrity level of the application.

The OTP_FCCU0_MODE[1:0] bits provide the default mode of operation for the FCCU0 pin.

OTP_FCCU0_MODE[1:0]

Operation

No operation

Single FCCU0 level monitoring

Single FCCU0 PWM monitoring

FCCU bistable monitoring

Table 204. FCCU0 mode selection bits

The OTP_FCCU1_MODE[1:0] bits provide the default mode of operation for the FCCU1 pin.

OTP_FCCU1_MODE[1:0]

Operation

No operation

Single FCCU1 level monitoring

Single FCCU1 PWM monitoring

XRESET operation

Table 205. FCCU1 mode selection bit

When the OTP_FCCU0_MODE[1:0] = 11, the FCCU0 and FCCU1 will operate in bistable mode, and the

OTP_FCCU1_MODE[1:0] bits will be used to decide whether the FCCU1 is operating in full FCCU mode or

hybrid mode.

When the FCCU interface is operating in bistable or hybrid mode, the FCCU configuration will be set with the

respective FCCU0 bits.

The default debounce time to detect an FCCU error is set in OTP via the OTP_FCCUx_DBNC[1:0] bits, and

the system can modify the debounce time during the SYSTEM ON states via the respective functional bits

FCCUx_DBNC[1:0].

FCCUx_DBNC[1:0]

FCCUx debounce time

3 μs

6 μs

12 μs

20 μs

Table 206. FCCUx debounce time configuration bit

The FCCUx_RESET[1:0] bits are provided to define whether the FCCUx fault should assert the FS0B only, or

generate a reset event.

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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