MPF0900AMMA2ES datasheet(140/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

All parameters are specified at TA = -40 °C to 125 °C, unless otherwise noted. Typical values are characterized at VIN = 5 V

and TA = 25 °C unless otherwise noted.

Symbol

Description

Min

Typ

Max

Unit

FIN_LF_FSYNC

FSYNC low frequency input range

• FSYNC_RANGE = 1

333

–

475

kHz

FIN_HF_FSYNC

FSYNC high frequency input range

• FSYNC_RANGE = 0

2.1

–

2.8

MHz

DIN_FSYNC

FSYNC input duty cycle range

–

Table 188. FSYNC electrical characteristics...continued

13.5 Analog multiplexer

The PF09 features a 32-channel analog multiplexer (AMUX) to allow a buffered access to various internal

voltages via the AMUX pin. An internal divider ratio is applied on each channel to ensure the AMUX output is

always within 1.65 V, making it suitable for 3.3 V or 1.8 V ADC inputs.

The AMUX_EN bit is provided to enable or disable the AMUX block.

AMUX_EN

AMUX block

AMUX disabled, pulled to ground

AMUX enabled.

Table 189. AMUX enable bit

The AMUX output is selected with the AMUX_SEL[4:0] bits.

AMUX_EN

AMUX_SEL[4:0]

AMUX Selection

Internal signal Dividing ratio

xxxxx

Disabled, pulled down

N/A

00000

Disabled - Hi-Z

N/A

00001

VIN

4.0

00010

BG REG

1.0

00011

BG MON

1.0

00100

VDIG

1.0

00101

VANA

1.0

00110

SW1_FB

1.0 (From 0.5 V to 1.5V)

2.5 (From 1.8 V to 3.3 V )

00111

SW2_FB

1.0 (From 0.5 V to 1.5 V)

2.5 (From 1.8 V to 3.3 V )

01000

SW3_FB

1.0 (From 0.5 V to 1.5 V)

2.5 (From 1.8 V to 3.3 V )

01001

SW4_FB

1.0 (From 0.3 V to 1.5 V)

2.5 (From 1.8 V to 3.3 V )

01010

SW5_FB

1.0 (From 0.3 V to 1.5 V)

2.5 (From 1.8 V to 3.3 V )

01011

LDO1

1.0 (from 0.75 V to 1.5 V)

Table 190. AMUX channel selection

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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