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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32H533CE датащи(PDF) 199 Page - STMicroelectronics |
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STM32H533CE датащи(HTML) 199 Page - STMicroelectronics |
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199 / 231 page  DS14539 Rev 1 199/231 STM32H533xx Electrical characteristics 200 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 118 and Table 119 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL= 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.14 for more details on the input/output characteristics: Table 118. Dynamic JTAG characteristics(1) 1. Evaluated by characterization - Not tested in production. Symbol Parameter Conditions Min Typ Max Unit FTCK TCK clock frequency 2.7 V < VDD < 3.6 V - - 47.5 MHz 1/tc(TCK) 1.71 V < VDD < 3.6 V - - 45 tisu(TMS) TMS input setup time - 3.5 - - ns tih(TMS) TMS input hold time - 1.5 - - tisu(TDI) TDI input setup time - 2.5 - - tih(TDI) TDI input hold time - 1.5 - - tov(TDO) TDO output valid time 2.7V < VDD < 3.6 V - 8 10.5 1.71 < VDD < 3.6 V - 8 11 toh(TDO) TDO output hold time - 6.5 - - Table 119. Dynamic SWD characteristics(1) 1. Evaluated by characterization - Not tested in production. Symbol Parameter Conditions Min Typ Max Unit FSWCLK SWCLK clock frequency 2.7 V < VDD < 3.6 V - - 80 MHz 1/tc(SWCLK) 1.71 V < VDD < 3.6 V - - 71 tisu(SWDIO) SWDIO input setup time - 1.5 - - ns tih(SWDIO) SWDIO input hold time - 1.5 - - tov(SWDIO) SWDIO output valid time 2.7 V < VDD < 3.6 V - 10.5 12.5 1.71 V < VDD < 3.6 V - 10.5 14.0 toh(SWDIO) SWDIO output hold time - 8.5 - - |
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