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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32H533CE датащи(PDF) 52 Page - STMicroelectronics |
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STM32H533CE датащи(HTML) 52 Page - STMicroelectronics |
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52 / 231 page  Functional overview STM32H533xx 52/231 DS14539 Rev 1 3.37 Universal synchronous/asynchronous receiver transmitter (USART/UART) and low-power universal asynchronous receiver transmitter (LPUART) The devices have four embedded universal synchronous receiver transmitters (USART1/USART2/USART3/USART6), two universal asynchronous receiver transmitters (UART4/UART5), and one low-power universal asynchronous receiver transmitter (LPUART1). Table 9. I3C peripheral controller/target features versus MIPI v1.1 Feature MIPI v1.1 When controller When target Comments I3C SDR message X X X - Legacy I2C message (Fm/Fm+) X X - Mandatory when controller, and the I3C bus is mixed with (external) legacy I2C target(s). Optional in MIPI v1.1 when target. HDR DDR message X - - Optional in MIPI v1.1 HDR-TSL/TSP, HDR-BT X - - Dynamic address assignment X X X - Static address X X - No (intended) support of I3C peripheral as a target on an I2C bus. Grouped addressing X X - Optional in MIPI v1.1 CCCs X X X Mandatory and some optional CCCs supported. Error detection and recovery X X X - In-band interrupt (with MDB) X X X - Secondary controller X X X - Hot-join mechanism X X X - Target reset X X X - Synchronous timing control X X - Optional in MIPI v1.1 Asynchronous timing control 0 X X - Asynchronous timing control 1, 2, 3 X - - Device to device tunneling X X - Multi-lane data transfer X X - Monitoring device early termination X - - Table 10. USART, UART and LPUART features Mode/feature(1) USART 1/2/3/6 UART 4/5 LPUART 1 Hardware flow control for modem X X X Continuous communication using DMA X X X |
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