STM32H533CE datasheet(47/231 Pages) STMICROELECTRONICS

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DS14539 Rev 1

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STM32H533xx

Functional overview

The timers can work together via the Timer Link feature for synchronization or event

chaining. The timers have independent DMA request generation.

The counters can be frozen in Debug mode.

3.33.3

Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit timebase.

3.33.4

Low-power timers

(LPTIM1, LPTIM2)

The devices embed six low-power timers. These timers have an independent clock and are

running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to

wake up the system from Stop mode.

The low-power timer supports the following features:

•

16-bit up counter with 16-bit autoreload register

•

3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)

•

Selectable clock

–

Internal clock sources: LSE, LSI, HSI or APB clock

–

External clock source over LPTIM input (working with no LP oscillator running,

used by Pulse Counter application)

•

16-bit ARR autoreload register

•

16-bit capture/compare register

•

Continuous/One-shot mode

•

Selectable software/hardware input trigger

•

Programmable digital glitch filter

•

Configurable output: pulse, PWM

•

Configurable I/O polarity

•

Encoder mode

•

Repetition counter

•

Up to two independent channels for:

–

Input capture

–

PWM generation (edge-aligned mode)

–

One-pulse mode output

•

Interrupt generation on ten events

•

DMA request generation on the following events:

–

Update event

–

Input capture

3.33.5

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently

from the main clock, it can operate in Stop and Standby modes. It can be used either as a

watchdog to reset the device when a problem occurs, or as a free running timer for

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