STM32H533CE datasheet(43/231 Pages) STMICROELECTRONICS

43 / 231 page

DS14539 Rev 1

43/231

STM32H533xx

Functional overview

•

Data swapping logic to support 1-, 8-, 16- or 32-bit data

•

Possibility for software to suspend a message if the SAES/AES needs to process

another message with a higher priority (suspend/resume operation)

3.30

HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm

(SHA-1, SHA-224, SHA-256, SHA-512) and the HMAC (keyed-hash message

authentication code) algorithm. HMAC is suitable for applications requiring message

authentication.

The HASH computes FIPS (Federal information processing standards) approved digests of

length of 160, 224, 256, 512 bits, for messages of up to (264 – 1).

The HASH main features are:

•

Suitable for data authentication applications, compliant with:

–

Federal Information Processing Standards Publication FIPS PUB 180-4, Secure

Hash Standard (SHA-1 and SHA-2 family)

–

Federal Information Processing Standards Publication FIPS PUB 186-4, Digital

Signature Standard (DSS)

–

Internet Engineering Task Force (IETF) Request For Comments RFC 2104,

HMAC: Keyed-Hashing for Message Authentication and Federal Information

Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message

Authentication Code (HMAC)

•

Fast computation of SHA-1, SHA-224, SHA-256 and SHA-512

–

82 (respectively 66) clock cycles for processing one 512-bit block of data using

SHA-1 (respectively SHA-256) algorithm

•

Corresponding 32-bit words of the digest from consecutive message blocks are added

to each other to form the digest of the whole message

–

Automatic 32-bit words swapping to comply with the internal little-endian

representation of the input bit string

–

Word swapping supported: bits, bytes, half-words and 32-bit words

•

Automatic padding to complete the input bit string to fit digest minimum block size of

512 bits (16 × 32 bits)

•

Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,

corresponding to one block size

Table 6. AES/SAES features

AES/SAES modes/features(1)

1. X = supported.

AES

SAES

ECB, CBC chaining

CTR, CCM, GCM chaining

AES 128-bit ECB encryption in cycles

528

DHUK and BHK key selection

Side-channel attacks resistance

Shared key between SAES and AES

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