STM32H533CE datasheet(54/231 Pages) STMICROELECTRONICS

54 / 231 page

Functional overview

STM32H533xx

54/231

DS14539 Rev 1

•

Auto baud rate detection

•

Programmable data word length (7, 8 or 9 bits)

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Programmable data order with MSB-first or LSB-first shifting

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Configurable stop bits (1 or 2 stop bits)

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Synchronous Master/Slave mode and clock output/input for synchronous

communications

•

SPI slave transmission underrun error flag

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Single-wire half-duplex communications

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Continuous communications using DMA

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Received/transmitted bytes are buffered in reserved SRAM using centralized DMA

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Separate enable bits for transmitter and receiver

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Separate signal polarity control for transmission and reception

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Swappable Tx/Rx pin configuration

•

Hardware flow control for modem and RS-485 transceiver

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Communication control/error detection flags

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Parity control:

–

Transmits parity bit

–

Checks parity of received data byte

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Interrupt sources with flags

•

Multiprocessor communications: wake-up from Mute mode by idle line detection or

address mark detection

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Autonomous functionality in Stop mode with wake-up from stop capability

•

LIN master synchronous break send capability and LIN slave break detection capability

–

13-bit break generation and 10/11 bit break detection when USART is hardware

configured for LIN

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IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode

•

Smartcard mode

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Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in

the ISO/IEC 7816-3 standard

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0.5 and 1.5 stop bits for Smartcard operation

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Support for Modbus communication

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Timeout feature

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CR/LF character recognition

3.37.2

Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum

power consumption. It also supports half-duplex single-wire communication and modem

operations (CTS/RTS). It allows multiprocessor communication.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to

9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame

while having an extremely low energy consumption. Higher-speed clock can be used to

reach higher baud-rates.

The LPUART interface can be served by the DMA controller.

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