STM32H533CE datasheet(27/231 Pages) STMICROELECTRONICS

27 / 231 page

DS14539 Rev 1

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STM32H533xx

Functional overview

•

Power management

–

Operating modes

–

Voltage scaling control

–

Low-power modes

•

VBAT battery charging

•

TrustZone security and privileged protection

3.10.1

Power supply schemes

The devices require a 1.71 to 3.6 V VDD operating voltage supply. Several independent

supplies can be provided for specific peripherals:

•

VDD = 1.71 V to 3.6 V

VDD is the external power supply for the I/Os, the internal regulator and the system

analog such as reset, power management and internal clocks. It is provided externally

through the VDD pins.

•

VDDA = 1.62 V (ADCs), 1.8 V (DACs), or 2.1 V (VREFBUF) to 3.6 V

VDDA is the external analog power supply for ADCs, DACs and voltage reference

buffer. This voltage level is independent from VDD, and must preferably be connected to

VDD when these peripherals are not used.

•

VDDUSB = 3.0 V to 3.6 V

VDDUSB is the external independent power supply for USB transceivers. It is

independent from VDD, and must preferably be connected to VDD when the USB is not

used.

•

VDDIO2 = 1.08 V to 3.6 V

VDDIO2 is the external power supply for 10 I/Os (PD6, PD7, PG9:14, PB8, PB9). This

voltage level is independent from VDD, voltage and must preferably be connected to

VDD when those pins are not used.

•

VBAT = 1.2 V to 3.6 V

VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers

(through power switch) when VDD is not present.

•

VREF-, VREF+

VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the

internal voltage reference buffer when enabled.

VREF+ can be grounded when ADC and DAC are not active.

VREF- and VREF+ pins are not available on all packages. When not available, they are

bonded to VSSA and VDDA, respectively.

When the VREF+ is double-bonded with VDDA in a package, the internal voltage

reference buffer is not available and must be kept disabled.

VREF- must always be equal to VSSA.

The devices embed an LDO regulator to provide the VCORE supply for digital peripherals,

SRAM1, SRAM2, SRAM3 and embedded flash memory. The LDO generates this voltage on

VCAP pin connected to an external capacitor of 2x 2.2 μF (typical).

This regulator can provide four different voltages (voltage scaling), and can operate in Stop

modes.

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