TMP93CS41 datasheet(207/248 Pages) TOSHIBA

207 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-205

3.13.2

Control Registers

The watchdog timer WDT is controlled by two control registers WDMOD and WDCR.

(1) Watchdog timer mode register (WDMOD)

1. Setting the detection time for the watchdog timer <WDTP>

This 2-bit register is used to set the watchdog timer interrupt time for detecting

runaway. This register is initialized to WDMOD<WDTP1:0>

= “00” when reset.

The detection time for WDT is shown in Figure 3.13.6.

2. Watchdog timer enable/disable control <WDTE>

When reset, WDMOD<WDTE> is initialized to “1” to enable the watchdog timer.

To disable the timer, it is necessary to clear this bit to “0” and write the disable code

(B1H) into the watchdog timer control register WDCR. This makes it difficult for the

watchdog timer to be disabled by runaway.

However, it is possible to return from the disabled state to the enabled state simply

by setting <WDTE> to “1”.

3. Watchdog timer out reset connection<RESCR>

This bit is used to connect the output of the watchdog timer with RESET internally.

Since WDMOD<RESCR> is initialized to “0” at reset, a watchdog timer reset is not

performed.

(2) Watchdog timer control register (WDCR)

This register is used to disable and clear the watchdog timer’s binary counter.

•

Disable control

The watchdog timer can be disabled by writing the disable code (B1H) to the WDCR

WDMOD

← 0 − − − − − X X

Clear WDMOD<WDTE> to “0”.

WDCR

← 1 0 11000 1

Write the disable code (B1H).

•

Enable control

This sets WDMOD<WDTE> to “1”.

•

Watchdog timer clear control

The binary counter can be cleared and made to resume counting by writing the clear

code (4EH) into the WDCR register.

WDCR

← 0 1 00111 0

Write the clear code (4EH).

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