TMP93CS41 datasheet(101/248 Pages) TOSHIBA

101 / 248 page

TMP93CS40/TMP93CS41

20004-02-10

93CS40-99

The timer clock selected among fFPH, fc/16, and fs is divided by 4 and input to this

prescaler. The selection is made by system clock control register SYSCR0<PRCK1:0>.

Resetting sets <PRCK1:0> to 00, which selects the fFPH clock input to be divided by 4.

The 8-bit timers 0 and 1 select among 4 clock inputs:

φT1, φT4, φT16, and φT256 of the

prescaler output.

This prescaler can be run or stopped by the timer control register TRUN<PRRUN>.

Counting starts when <PRRUN> is set to “1”. The prescaler is cleared to zero and stops

operation when <PRRUN> is set to “0”.

Resetting clears <PRRUN> to “0” and stops the prescaler.

When the IDLE1 mode (in which only the oscillator operates) is used, set TRUN

<PRRUN> to “0” to reduce the power consumption of the prescaler before the “HALT”

instruction is executed.

2. Up counter

This is an 8-bit binary counter which counts up by the input clock pulse specified by

TMOD.

The input clock of timer 0 is selected from among the external clock from the TI0 pin, and

the three internal clocks

φT1, φT4, and φT16, according to the value set in the TMOD

The input clock used by timer 1 depends on the operation mode. When 16-bit timer mode

is set, the overflow output of timer 0 is used as the input clock. When any mode other than

16-bit timer mode is set, the input clock is selected from among the internal clocks

φT1,

φT16, and φT256 as well as the comparator output (Match detection signal) of timer 0

according to the set value of the TMOD register.

Example: When TMOD<T10M1:0>

= 01, the overflow output of timer 0 becomes the

input clock of timer 1 (16-bit timer mode).

When TMOD<T10M1:0>

= 00 and TMOD<T1CLK1:0> = 01, φT1 becomes the

input of timer 1 (8-bit timer mode).

Similarly, operation mode is also set by the TMOD register. When reset, it is initialized to

TMOD<T01M1:0>

= 00 whereby the up counter is placed in the 8-bit timer mode.

The counting and stop and clear of the up counter can be controlled for each interval

timer by the timer operation control register TRUN. When reset, all up counters will be

cleared to stop the timers.

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