TMP93CS32F datasheet(19/180 Pages) TOSHIBA

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TMP93CS32

2004-02-10

93CS32-17

Table 3.3.2 I/O Operation during HALT Mode

HALT Mode

RUN

IDLE2

IDLE1

STOP

WDMOD<HALTM1:0>

CPU

Stop

I/O port

Keep the state when the “HALT” instruction was executed.

See Table 3.3.5

8-Bit timer

16-Bit timer

Serial channel

AD converter

Operate

Stop

Watchdog timer

Interrupt controller

(2) How to release the HALT mode

These halt states can be released by resetting or requesting an interrupt. The halt

release sources are determined by the combinations between the states of interrupt

mask register <IFF2:0> and the HALT modes. The details for releasing the halt status

are shown in Table 3.3.3.

•

Released by requesting an interrupt

The operating released from the HALT mode depends on the interrupt enabled

status. When the interrupt request level set before executing the HALT instruction

exceeds the value of the interrupt mask register, the interrupt due to the source is

processed after releasing the HALT mode, and CPU starts executing an instruction

that follows the HALT instruction. When the interrupt request level set before

executing the HALT instruction is less than the value of the interrupt mask

interrupt processing is processed after releasing the HALT mode regardless of the

value of the mask register.)

However only for INT0 interrupts, even if the interrupt request level set before

executing the HALT instruction is less than the value of the interrupt mask

not processed, and CPU starts executing the instruction next to the HALT

instruction, but the interrupt request flag is held at “1”.

Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,

INT0) which can release the HALT mode may not be able to do so if they are

input during the period CPU is shifting to the HALT mode (for about 3 clocks of

fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case) (In

this case, an interrupt request is kept on hold internally)

If another interrupt is generated after it has shifted to HALT mode completely, halt

status can be released without difficultly. The priority of this interrupt is compare

with that of the interrupt kept on hold internally, and the interrupt with higher

priority is handled first followed by the other interrupt.

•

Release by resetting

Releasing all halt status is executed by resetting.

When the STOP mode is released by RESET, it is necessary enough resetting

time (3 ms or more) to set the operation of the oscillator to be stable.

When releasing the HALT mode by resetting, the internal RAM data keeps the

state before the HALT instruction is executed. However the other setting contents

are initialized. (Releasing due to interrupts keep the state before the HALT

instruction is executed.)

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