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TMP93CS32F датащи(PDF) 15 Page - Toshiba Semiconductor |
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TMP93CS32F датащи(HTML) 15 Page - Toshiba Semiconductor |
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15 / 180 page ![]() TMP93CS32 2004-02-10 93CS32-13 3.3.1 System Clock Controller The system clock controller generates system clock (fSYS) for CPU core and internal I/O. It contains a oscillation circuit and clock gear circuit. The register SYSCR1<GEAR2:0> changes clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16), and these functions can reduce the power consumption of the equipment in which the device is installed. The system clock (fSYS) is set to fc/32 (fc/16 × 1/2) because of <GEAR2:0> = “100” by resetting. For example, fSYS is set to 0.625 MHz by resetting the case of 20 MHz oscillator is connected to X1, X2 pins. The fc clock can be easily obtained by connecting a resonator to the X1/X2 pins respectively. Clock input from an external oscillator is also possible. Figure 3.3.4 Examples of Resonator Connection * Accurate adjustment of the oscillation frequency The CLK pin outputs at 1/2 the system clock frequency (fSYS/2) is used to monitor the oscillation clock. With a system requiring adjustment of the oscillation frequency, an adjusting program must be written. X1 X2 X1 X2 74HCU04 (a) Crystal/Ceramic resonator (b) External oscillator |
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