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TMP93CS32F датащи(PDF) 39 Page - Toshiba Semiconductor

номер детали TMP93CS32F
подробное описание детали  CMOS 16-Bit Microcontroller
PDF  180 Pages
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производитель  TOSHIBA [Toshiba Semiconductor]
домашняя страница  http://www.semicon.toshiba.co.jp/eng
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TMP93CS32F датащи(HTML) 39 Page - Toshiba Semiconductor

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TMP93CS32
2004-02-10
93CS32-37
(1) Interrupt priority setting register
Symbol
Address
7
6
5
4
3
2
1
0
INTAD
INT0
IADC
IADM2
IADM1
IADM0
I0C
I0M2
I0M1
I0M0
R/W
W
R/W
W
INTE0AD
0070H
0
0
0
0
0
0
0
0
INT5
INT4
I5C
I5M2
I5M1
I5M0
I4C
I4M2
I4M1
I4M0
R/W
W
R/W
W
INTE45
0071H
0
0
0
0
0
0
0
0
INT7
INT6
I7C
I7M2
I7M1
I7M0
I6C
I6M2
I6M1
I6M0
R/W
W
R/W
W
INTE67
0072H
0
0
0
0
0
0
0
0
INTT1 (Timer1)
INTT0 (Timer0)
IT1C
IT1M2
IT1M1
IT1M0
IT0C
IT0M2
IT0M1
IT0M0
R/W
W
R/W
W
INTET10
0073H
0
0
0
0
0
0
0
0
INTT3 (Timer3)
INTT2 (Timer2)
IT3C
IT3M2
IT3M1
IT3M0
IT2C
IT2M2
IT2M1
IT2M0
R/W
W
R/W
W
INTET32
0074H
0
0
0
0
0
0
0
0
INTTR5 (TREG5)
INTTR4 (TREG4)
IT5C
IT5M2
IT5M1
IT5M0
IT4C
IT4M2
IT4M1
IT4M0
R/W
W
R/W
W
INTET54
0075H
0
0
0
0
0
0
0
0
INTTR7 (TREG7)
INTTR6 (TREG6)
IT7C
IT7M2
IT7M1
IT7M0
IT6C
IT6M2
IT6M1
IT6M0
R/W
W
R/W
W
INTET76
0076H
0
0
0
0
0
0
0
0
INTTO5
INTTO4
ITO5C
ITO5M2
ITO5M1
ITO5M0
ITO4C
ITO4M2
ITO4M1
ITO4M0
R/W
W
R/W
W
INTEO54
0077H
0
0
0
0
0
0
0
0
INTTX0
INTRX0
ITX0C
ITX0M2
ITX0M1
ITX0M0
IRX0C
IRX0M2
IRX0M1
IRX0M0
R/W
W
R/W
W
INTES0
0078H
0
0
0
0
0
0
0
0
INTTX1
INTRX1
ITX1C
ITX1M2
ITX1M1
ITX1M0
IRX1C
IRX1M2
IRX1M1
IRX1M0
R/W
W
R/W
W
INTES1
0079H
0
0
0
0
0
0
0
0
IxxM2
IxxM1
IxxM0
Function (Write)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Prohibits interrupt request.
Sets interrupt request level to “1”.
Sets interrupt request level to “2”.
Sets interrupt request level to “3”.
Sets interrupt request level to “4”.
Sets interrupt request level to “5”.
Sets interrupt request level to “6”.
Prohibits interrupt request.
IxxC
Function (Read)
Function (Write)
0
Indicates no interrupt request.
Clears interrupt request flag.
1
Indicates interrupt request.
- - - - - Don’t care - - - - -
Note 1:
Read-modify-write is prohibited.
Note 2:
Note about clearing interrupt request flag
The interrupt request flag of INTRX0, INTRX1 are not cleared by writing “00” to IXXC because of they are
level interrupts. They can be cleared only by resetting or reading SCBUFn.
Figure 3.4.5 Interrupt Priority Setting Register
←Interrupt source
←Bit symbol
←Read/Write
←After reset



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