TMP93CS32F datasheet(62/180 Pages) TOSHIBA

62 / 180 page

TMP93CS32

2004-02-10

93CS32-60

3.6

Bus Width/Wait Controller, AM8/ AM16 Pin

TMP93CS32 has a built-in controller used to control wait ( WAIT pin) and data bus size (8 or

16 bits) for any of the three block address areas.

3.6.1

AM8/ AM16 Pin

Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus width.

The bus width when the CPU accesses an external area is set by the bus width/wait cntrol

registers (Described at 3.6.3) and the registers of Port 1. (The value “1” of this pin is ignored

and the value set by register is active.)

3.6.2

Address/Data Bus Pins

Port 0/AD0 to AD7, Port 1/AD8 to AD15/A8 to A15 and Port 2/A16 to A23/A0 to A7

function as address/data bus for connecting the external memories.

Number of address

bus pins

Max 24 (to 16 Mbytes)

Max 16 (to 64 Kbytes)

Max 8 (to 256 bytes)

Number of data bus

pins

Number of

multiplexed pins

VIH

Mode

pins

AM8/

VIH

Port 0

AD0 to AD7

Port 1

A8 to A15

AD8 to AD15

A8 to A15

AD8 to AD15

Port

function

Port 2

A16 to A23

A0 to A7

Timing chart

Note 1: In case of 3 and 4, the data bus signals output the addresses since the signals are also

used as the address bus. Writing “0” to bit CKOCR<ALEEN>, ALE signal can be

stopped outputting.

Note 2: After reset operation, Port 0, Port 1, and Port 2 function as Input ports, not as address,

data bus signals.

A23 to 8

to 0

A23 to 8

AD7 to 0

to 0

ALE

A23 to 16

A15

to 0

A23 to 16

AD15 to 0

D15

to 0

ALE

A15 to 0

to 0

A15 to 0

AD7 to 0

to 0

ALE

(note1)

A7 to 0

A15

to 0

A7 to 0

AD15 to 0

D15

to 0

ALE

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