TMP93CS32F datasheet(36/180 Pages) TOSHIBA

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TMP93CS32

2004-02-10

93CS32-34

(3) Transfer mode register details

Mode

Execution time

(Min) at 20 MHz

Z: 0

= Byte transfer, 1 = Word transfer

Transfer destination address INC mode for I/O to memory

(DMADn

+) ← (DMASn)

DMACn

← DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Transfer destination address DEC mode for I/O to memory

(DMADn

−) ← (DMASn)

DMACn

← DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Transfer source address INC mode...........for memory to I/O

(DMADn)

← (DMASn+)

DMACn

← DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Transfer source address DEC mode .........for memory to I/O

(DMADn)

← (DMASn−)

DMACn

← DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Fixed address mode...............................................I/O to I/O

(DMADn)

← (DMASn)

DMACn

← DMACn − 1

if DMACn

= 0 then INT.

16 states

(1.6

µs)

Counter mode ....................................... for interrupt counter

DMASn

← DMASn + 1

DMACn

← DMACn − 1

if DMACn

= 0 then INT.

11 states

(1.1

µs)

(1 states

= 100 ns at 20 MHz, high frequency mode)

Note 1:

n: Corresponds to micro DMA channels 0 to 3.

DMADn

+/DMASn+: Post-increment (Increments register value after transfer.)

DMADn

−/DMASn−: Post-decrement (Decrement register value after transfer.)

Note 2:

Execution time: When setting source address/destination address area to 16-bit bus, 0 waits.

Clock condition: fc

= 20 MHz, clock gear: 1(fc)

Note 3:

Do not use the codes other than the above mentioned codes for transfer mode register.

Note: When setting values for this

(DMAM0 to DMAM3)

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