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TMP93CS32F датащи(PDF) 95 Page - Toshiba Semiconductor |
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TMP93CS32F датащи(HTML) 95 Page - Toshiba Semiconductor |
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95 / 180 page ![]() TMP93CS32 2004-02-10 93CS32-93 Timer 4, 5 Control Register 7 6 5 4 3 2 1 0 Bit symbol QCU DB6EN DB4EN T45CR (003AH) Read/Write R/W R/W After reset 0 0 0 Double buffer 0: Disable 1: Enable Function Watchdog/ Warm-up timer control Double buffer of TREG6 Double buffer of TREG4 Double buffer control 0 Disable 1 Enable DB6EN: Double buffer of TREG6 DB4EN: Double buffer of TREG4 Watchdog timer/warm-up timer input control 0 Use 7 stage binary counter 1 Not use 7 stage binary counter (Note1) Note 1: In case of unused 7 state binary counter as a warm-up timer, the stable clock must be input from external circuit. Note 2: Bit6 to 2 of T45CR are read as “1”. Figure 3.8.7 16-Bit Timer/Event Counter Related Register (5/6) |
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