TMP93CS32F datasheet(18/180 Pages) TOSHIBA

18 / 180 page

TMP93CS32

2004-02-10

93CS32-16

3.3.4

Standby Controller

(1) HALT mode

When the HALT instruction is executed, the operating mode changes RUN, IDLE2,

IDLE1, or STOP mode depending on the contents of the HALT mode setting register

WDMOD<HALTM1:0>. Figure 3.3.5 shows the alternative states of the watchdog

timer mode registers.

Watchdog Timer Mode Register

Bit symbol

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

Read/Write

R/W

After reset

Function

Watchdog

timer

control

0: Disable

1: Enable

Watchdog timer

detect time selection

00: 2

15/fSYS

01: 2

17/fSYS

10: 2

19/fSYS

11: 2

21/fSYS

Warm-up

timer

0: 2

14/clock

frequency

selection

1: 2

16/clock

frequency

selection

Halt mode selection

00: RUN mode

01: STOP mode

10: IDLE1 mode

11: IDLE2 mode

Runaway

detection

internal

reset

control

1: Executes

internal

reset by

runaway

detection

STOP

mode pin

control

1: Drive

pins in

STOP

mode

Pin state control in STOP mode

I/O off

Retains the state before halt

HALT mode setting

RUN mode (only CPU stop)

STOP mode (all circuits stop)

IDLE1 mode (only oscillator operating)

IDLE2 mode (partial I/O operating)

Warm-up time selection at returning from the

stop mode (see Table 3.3.4)

14/select clock frequency

216/select clock frequency

Figure 3.3.5 Watchdog Timer Mode Register

The futures of RUN, IDLE2, IDLE1, and STOP modes are as follows.

RUN: Only the CPU halts; power consumption remains unchanged.

IDLE2: The built-in oscillator and the specified I/O operates.

The power consumption is redced to 1/2 than that during NORMAL

operation.

IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop.

The power consumption is reduced to 1/5 or less than that during

NORMAL operation.

STOP: All internal circuits including the built-in oscillator stop. This greatly

reduces power consumption.

The operations in the halt state is described in Table 3.3.2.

WDMOD

(005CH)

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